AI Accelerators · Compiler IRs · Equality Saturation

Compiler engineer building infrastructure for emerging hardware.

I build compiler systems for accelerators, FPGAs, managed runtimes, and MLIR tooling. My work focuses on IR design, hardware-aware compilation, and optimization techniques including equality saturation.

Published At
CGO 2026 · CC 2026 · CGO 2024
Built Systems For
e-graphs · FPGAs · MLIR · managed runtimes
Results
16x speedup in Foresight; expert-level FPGA designs in SkeleShare

Now

Research-grade ideas, engineered as usable compiler infrastructure.

I recently joined Cerebras as a compiler engineer, where I work on compiler infrastructure for AI accelerator systems. Alongside that, my PhD research at McGill University and Mila, with Christophe Dubach, turns equality saturation and compact functional IRs into tools for parallel rewriting, FPGA design search, and library idiom recognition.

Guide

Areas of focus

Equality saturation at scale

Foresight makes e-graphs parallel and programmable; Latent Idiom Recognition uses equality saturation to recover hidden high-performance library calls.

Hardware-aware compilation

SkeleShare searches hardware resource-sharing designs with equality saturation, solver-based extraction, and hardware-conscious program structure for FPGAs.

Compiler infrastructure

MLIR.NET, Flame, and the Julia GPU garbage collector cover typed IR APIs, SSA optimization, LLVM lowering, managed runtimes, and GPU runtime support.