Equality saturation at scale
Foresight makes e-graphs parallel and programmable; Latent Idiom Recognition uses equality saturation to recover hidden high-performance library calls.
Compilers · IRs · Equality Saturation
Compiler engineer building compilers for new hardware.
I build compilers for emerging systems, including accelerators, FPGAs, managed runtimes, and MLIR tooling. My work focuses on IR design and novel optimization techniques, including equality saturation.
- Published At
- CGO 2026 · CC 2026 · CGO 2024
- Built Systems For
- e-graphs · FPGAs · MLIR · managed runtimes
- Results
- 16x speedup in Foresight; expert-level FPGA designs in SkeleShare
Current Focus
Research-grade ideas, engineered as usable compiler infrastructure.
I am a PhD candidate at McGill University, affiliated with Mila, working with Christophe Dubach. My recent work turns equality saturation and compact functional IRs into tools for parallel rewriting, FPGA design search, and library idiom recognition.
Guide
Areas of focus
Hardware-aware compilation
SkeleShare searches FPGA resource-sharing designs with equality saturation, solver-based extraction, and hardware-conscious program structure.
Compiler infrastructure
MLIR.NET, Flame, and the Julia GPU garbage collector cover typed IR APIs, SSA optimization, LLVM lowering, managed runtimes, and GPU runtime support.
Featured Systems
Recent compiler research
CC 2026
Foresight
A parallel, extensible equality saturation library with programmable saturation strategies, generalized e-graph metadata, and deferred parallel rewriting.
- Impact
- Up to 16x speedup
- Role
- Designed and implemented the core system
- Scala
- e-graphs
- parallel rewriting
- IR metadata
CGO 2026
SkeleShare
Automates hardware resource allocation and sharing by combining equality saturation, algorithmic skeletons, and solver-based extraction.
- Impact
- Matches or exceeds expert designs
- Role
- Equality-saturation system for hardware design search
- FPGA
- HLS
- equality saturation
- solver extraction